1. Field of the Invention
The present invention relates to a process used to fabricate dynamic random access memory, (DRAM), devices, and more specifically to a fabrication process in which the area of the DRAM cell is reduced by stacking the capacitor structure over the access transistor.
2. Description of the Prior Art
In order to satisfy demands for high density DRAM semiconductor chips, micro-miniaturization, or the use of sub-micron features, used for DRAM designs, are employed. The attainment of micro-miniaturazation, or sub-micron features, has been mainly accomplished by advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be created in photoresist layers. In addition the development of more advanced dry etching tools and etch recipes, have allowed the sub-micron images in overlying photoresist layers to be successfully transferred to underlying materials, used in the creation of advanced semiconductor devices.
However to achieve DRAM densities of 256 megabits, or greater, new designs may be needed. Currently the area needed for a DRAM cell is equal to about eight times the minimum feature used, sometimes referred to as 8F.sup.2. The creation of DRAM devices, with an area only four times the minimum used feature, 4F.sup.2, is limited by two basic elements in the DRAM cell, the word line transistor and the storage capacitor. These two elements can not use the same space on the semiconductor chip, if 4F.sup.2 is to be realized. To achieve a DRAM area of 4F.sup.2 these two elements have to be aligned vertically.
This invention will describe a fabrication process for a DRAM cell, in which 4F.sup.2 is achieved by vertically aligning the polysilicon capacitor structure and the gate polysilicon structure, while using an underlying bit line, embedded in the device isolation insulator. Prior art, such as Dhong, et al, describe a method for forming a folded bit line DRAM cell, however that process differs from the present invention in many key areas, such as their use of polysilicon filled trenches, as capacitors.